(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to increase the surface area of a capacitor structure.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices using sub-micron features, has allowed the performance of these devices to be increased while the cost of manufacturing these same devices has decreased. Smaller semiconductor chips, still offering device densities equal to, or greater than, device densities achieved with larger size semiconductor chips, have allowed the fabrication cost of a specific chip to be reduced. However the smaller semiconductor chips, such a dynamic random access memory (DRAM) chips, are now comprised with smaller individual transfer gate transistors, which in turn commit less horizontal space for the DRAM stacked capacitor structures. Therefore to satisfy capacitance requirements novel designs for DRAM capacitor structures, featuring increased vertical features needed to compensate for the decreased horizontal features now necessitated with sub-micron DRAM devices, have been employed. Storage node components, of DRAM capacitor structures, have been fabricated with fin type features, crown shaped features, and cylindrical shaped features, in an attempt to increase the surface area of a DRAM capacitor structure which now directly overlays a horizontally shrinking, underlying DRAM transfer gate transistor component.
The processes needed to fabricate DRAM capacitor structures, comprised with fin type, crown shaped, or cylindrical type features, although resulting in the desired increase in capacitor surface are, however do increase process complexity and cost. The present invention will describe a novel process for increasing capacitor surface area, without the complex and costly processes needed for the DRAM capacitor structures comprised with fin, crown and cylindrical shapes. This invention will describe a process in which the desired, increased capacitor surface area is obtained via conventional formation of a storage node structure, in a storage node contact hole opening, however with the storage node opening formed in a specific type insulator layer, and subjected to specific process steps prior to accommodation of the storage node structure. Prior art such as Hayashide et al, in U.S. Pat. No. 5,318,920, as well as Tseng, in U.S. Pat. No. 6,140,178, describe methods of increasing the surface area of DRAM capacitor structures, however these prior arts do not use the novel approach described in this invention entailing the formation of a storage node opening formed in a porous insulator layer.
It is an object of this invention to fabricate a capacitor structure for a DRAM device.
It is another object of this invention to increase the surface area of DRAM storage node structure by forming this structure in a storage node opening comprised with sidewall crevices and grooves.
It is still another object of this to form the crevices and grooves in the sidewall of the storage node opening via formation of the storage node opening in a porous insulator layer, followed by wet etch procedures used to enlarge the crevices and grooves.
In accordance with the present invention a method of forming a storage node structure for a DRAM capacitor structure, in a storage node opening which has been defined in a porous insulator layer, featuring grooves and crevices located in the sides of the storage node opening, enabling increases in storage node surface area to be achieved, is described. After formation of conductive plug structures in openings in an insulator layer, contacting underlying conductive regions of a DRAM transfer gate transistor, a porous insulator layer is deposited. Storage node openings are next defined in the porous insulator layer exposing the top surface of the underlying conductive plug structures, and exposing small grooves, or crevices, located in the sides of the storage node openings, extending into the porous insulator layer, with the small grooves formed from exposure of voids in the porous insulator layer, during the dry etching, storage node opening procedure. A subsequent wet etch procedure is then used to enlarge the small grooves and crevices, resulting in a storage node opening featuring large grooves and crevices extending into the porous insulator layer. Deposition of a polysilicon layer results in a storage node structure contacting the underlying storage node plug structure, as well as located on the sides of, including in the large crevices and grooves of, the storage node opening. Formation of a capacitor dielectric layer, on the storage node structure, and of an upper electrode structure, results in a DRAM capacitor structure with increased capacitor surface area as a result of the grooves and crevices formed in the sides of a storage node opening, which in turn was formed in a porous insulator layer.